Unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
Process variation (PV) in IC manufacturing refers to the deviation of IC parameter values from nominal specifications, due to the nature of the manufacturing process generally. The presence of PV in deep submicron technologies has become a major concern for Integrated Circuit (IC) energy optimization attempts. Some existing pre-silicon IC optimization to compensate for the impact of PV apply statistical analysis to capture the PV influence and compensate for the influence in the IC design. These approaches generally are not generic to various designs and technologies, and they can be greatly impacted by random components, such as environment temperatures, which may not be timely reflected in the design models.
Some post-silicon optimization approaches also exist to address the aforementioned issues that the pre-silicon optimization approaches are unable to resolve. However, the existing approaches do not take into consideration any IC aging effect caused by low energy input vectors. In particular, IC aging has long been considered as a detrimental phenomenon to IC design and operation, because it may cause an increase in the threshold voltage, and thus it may result in a delay degradation over time. However, the threshold voltage increase brought by IC aging may cause the leakage energy of a gate to decrease.
Accordingly, methods and systems are described herein to utilize IC aging to reduce leakage energy consumption of a target circuit during the operations of the target circuit.